This invention relates to reference voltage sources and particularly to on-chip current stacked band gap reference voltage sources.
On-chip voltage reference sources employ voltage stacked bipolar transistor array bandgap structures to derive reference voltages for use on the chip. Stacked bipolar arrays reduce sensitivity to operational amplifier offsets, resistor mismatches, and current mirror mismatches, without employing laser trimming or autozeroing clocks. One advantage of a stacked array is that a large .DELTA.Vbe voltage can be derived to enhance the tolerance of the circuit by minimizing errors due to offsets and mismatches due to reduced gain to the output.
Stacked reference voltage sources reduce the effect of error voltages, such as offset due to amplifier, resistor and current mirror mismatches, by increasing the contribution of the .DELTA.Vbe voltage. By employing an area-ratioed stack of matched bipolar transistors, a +TC reference voltage is produced which is N times the .DELTA.Vbe voltage, where N is the number of stacks in the array. The +TC voltage is proportional to K (N.DELTA.Vbe+Vos) where Vos is the error voltage due to offset. Thus, the offset is effectively reduced by a factor of N. It will be appreciated that the error voltage is multiplied by the constant K, but the constant K may be reduced by increasing the number of levels in the stack of the array. See Ahuja et al., "A Programmable CMOS Dual Channel Interface Processor for Telecommunications Applications", IEEE Journal on Solid-State Circuits, Vol. SC-19, No. 6, pp. 892-899 (December 1984).
However, voltage stacked bipolar transistor arrays require significant supply headroom for operation. For example, three stacked Vbe diode drops of an array of three bipolar transistors requires approximately a headroom of 2.1 volts (assuming 0.7 volt diode drops). Moreover, the transistors exhibit a temperature coefficient of about -2 mV/.degree. C., so when operating at extreme temperature conditions (such as -50.degree. C.), the required supply headroom increases to approximately 2.55 volts for three diode drops. While reducing the stack size to two transistors reduces the required supply headroom to about 1.4 volts (1.7 volts at -50.degree. C.), the reduction of the array size requires increasing constant K to achieve the desired reference voltage, and is not as effective in reducing sensitivity to offsets and mismatches. Further, in modern IC processes, where power supplies may he of the order of 1.8 volts .+-.10%, voltage stacked arrays are not realizable.